1. Field of the Invention
The present invention relates to a hybrid silicon wafer comprising the functions of both a polycrystalline silicon wafer and a single-crystal wafer, and to the method of manufacturing such a hybrid silicon wafer.
2. Description of the Related Art
In the silicon semiconductor manufacturing process, a wafer prepared based on single-crystal growth is primarily used. This single-crystal silicon wafer has increased in size with the times, and it is anticipated that the inner diameter will become φ400 mm or larger in the near future. In addition, a so-called mechanical wafer for testing is now required in order to establish the apparatus and peripheral technology necessary for the semiconductor manufacturing process.
Generally speaking, since this kind of mechanical wafer is subject to fairly high precision testing, it needs to possess characteristics that are similar to the mechanical physicality of single-crystal silicon. Thus, conventionally, although it was to be used for testing, in reality the single-crystal silicon wafer was being used as is. However, since a single-crystal silicon wafer having an inner diameter of φ400 mm or larger is extremely expensive, an inexpensive wafer having characteristics that are similar to single-crystal silicon is in demand.
Meanwhile, as a component of such semiconductor manufacturing equipment, a proposal has also been made for using a sputtering target formed from a rectangular or disk-shaped silicon plate. The sputtering method is being used as a means for forming thin films, and there are several sputtering methods including the bipolar DC sputtering method, radio frequency sputtering method, magnetron sputtering method and the like, and thin films of various electronic parts are being formed using the sputtering characteristics unique to the respective methods.
This sputtering method is a method that faces a substrate as the anode and a target as the cathode, and generates an electrical field by applying a high voltage between the foregoing substrate and target under an inert gas atmosphere. Here, the ionized electrons and inert gas collide to form a plasma, the cations in the plasma collide with the target surface to hammer out the target constituent atoms, and the discharged atoms adhere to the opposite substrate surface so as to form a film.
A polycrystalline silicon sintered compact is proposed for this kind of sputtering target, and this sintered compact target is demanded of considerable thickness and of being large-size rectangular or disk-shaped in order to improve the deposition efficiency. Moreover, a proposal has also been made for using this polycrystalline silicon sintered compact as a board for retaining the single-crystal silicon wafer. Nevertheless, polycrystalline silicon entails significant problems in that the sinterability is inferior, the obtained products have low density, and the mechanical strength is low.
In light of the above, in order to improve the characteristics of the foregoing silicon sintered compact, proposed is a silicon sintered compact formed by compression-molding and sintering silicon powder obtained by being heated and deoxidized under reduced pressure and within a temperature range that is 1200° C. or higher and less than the melting point of silicon, and setting the crystal grain size of the sintered compact to be 100 μm or less (for instance, refer to Japanese Patent No. 3342898).
If the thickness of the silicon sintered compact manufactured as described above is thin; for instance, 5 mm or less, the density will relatively increase and the strength will also increase, however, if the thickness becomes thicker, the density will continue to be a low density (less than 99%), and the mechanical strength will also deteriorate. Thus, it is a problem that manufacturing a large-size rectangular or disk-shaped silicon sintered compact is not possible.
In light of the foregoing circumstances, the present applicant previously proposed a silicon sintered compact and its production method in which the average crystal grain size is 50 μm or less and the relative density is 99% or more (refer to Japanese Patent No. 3819863).
Although this silicon sintered compact possesses numerous advantages including high density and high mechanical strength, the further improvement of these characteristics is being demanded, and the applicant filed a patent application relating to technology that improved the foregoing points.
Since a wafer using the foregoing silicon sintered compact has similar mechanical properties as single-crystal silicon, it can be used as a dummy wafer for the transport system of semiconductor manufacturing equipment or the development of robotics. In addition, the application of an SOI wafer as a base substrate is also being considered.
Nevertheless, these are all polycrystalline silicons made from a silicon sintered compact, and although there are numerous points that are similar to the physical properties of a single crystal, they do not possess the function as the single crystal itself, and there is a fundamental problem in that they cannot be used for process testing such as deposition experiments.
Moreover, there is also a proposal of manufacturing a high quality polycrystalline silicon in substitute for single-crystal silicon (refer to Japanese Patent Published Unexamined Application No. 2005-132671). Nevertheless, polycrystalline silicon has a drawback in that, no matter what kind of devisal is made, its characteristics will be inferior to single-crystal silicon. As a means for overcoming this drawback, M. Goldstein of Intel and others proposed a wafer in which single-crystal silicon is embedded in polycrystalline silicon (refer to US Patent Publication No. 2008/0122042).
Moreover, the present applicant previously filed an application for an invention which uses silicon prepared with the sintering method at the polycrystalline portion of the wafer in which single-crystal silicon is embedded in the foregoing polycrystalline silicon. However, the sintered silicon contains large amounts of gas components such as oxygen and carbon, and since precipitates of SiO2 and SiC exist at the crystal grain boundary, there is a problem in that unevenness will occur during the polishing due to the difference in the polishing rate compared to the single-crystal portion (refer to International Publication No. WO2010-004863).
In light of the above, the present applicant proposed manufacturing a hybrid silicon wafer by hollowing a part of a polycrystalline silicon prepared in advance based on the unidirectional solidification/melting method, inserting a single-crystal silicon ingot into the hollowed portion, performing thermal diffusion bonding thereto in order to prepare a complex of a polycrystalline silicon and a single-crystal silicon ingot, and slicing the complex to manufacture a hybrid silicon wafer (refer to Japanese Patent Application No. 2009-255016).
Although this method is less costly than a wafer in which the entire surface is formed of a single crystal, it is necessary to strictly control the tolerance of the hollowing process of the polycrystalline and the edge processing of the single-crystal to be embedded, and there is a problem in that this led to the increase in production costs.